Binding for simple mux clock.

This binding uses the common clock binding[1].  It assumes a
register-mapped multiplexer with multiple input clock signals or
parents, one of which can be selected as output.  This clock does not
gate or adjust the parent rate via a divider or multiplier.

By default the "clocks" property lists the parents in the same order
as they are programmed into the regster.  E.g:

	clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;

results in programming the register as follows:

register value		selected parent clock
0			foo_clock
1			bar_clock
2			baz_clock

Some clock controller IPs do not allow a value of zero to be programmed
into the register, instead indexing begins at 1.  The optional property
"index-starts-at-one" modified the scheme as follows:

register value		selected clock parent
1			foo_clock
2			bar_clock
3			baz_clock

Additionally an optional table of bit and parent pairs may be supplied
like so:

	table = <&foo_clock 0x0>, <&bar_clock, 0x2>, <&baz_clock, 0x4>;

where the first value in the pair is the parent clock and the second
value is the bitfield to be programmed into the register.

The binding must provide the register to control the mux and the mask
for the corresponding control bits.  Optionally the number of bits to
shift that mask if necessary.  If the shift value is missing it is the
same as supplying a zero shift.

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible : shall be "mux-clock".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link phandles of parent clocks
- reg : base address for register controlling adjustable mux
- bit-mask : arbitrary bitmask for programming the adjustable mux

Optional properties:
- clock-output-names : From common clock binding.
- table : array of integer pairs defining parents & bitfield values
- bit-shift : number of bits to shift the bit-mask, defaults to
  (ffs(mask) - 1) if not present
- index-starts-at-one : valid input select programming starts at 1, not
  zero
- hiword-mask : lower half of the register programs the mux, upper half
  of the register indicates bits that were updated in the lower half

Examples:
	clock: clock@4a008100 {
		compatible = "mux-clock";
		#clock-cells = <0>;
		clocks = <&clock_foo>, <&clock_bar>, <&clock_baz>;
		reg = <0x4a008100 0x4>
		mask = <0x3>;
		index-starts-at-one;
	};

	clock: clock@4a008100 {
		#clock-cells = <0>;
		compatible = "mux-clock";
		clocks = <&clock_foo>, <&clock_bar>, <&clock_baz>;
		reg = <0x4a008100 0x4>;
		mask = <0x3>;
		shift = <0>;
		table = <&clock_foo 1>, <&clock_bar 2>, <&clock_baz 3>;
	};
