
/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 6.2.2 EDK_Gm.13.6
* DO NOT EDIT.
*
* Copyright (c) 2003 Xilinx, Inc.  All rights reserved. 
* 
* Description: Driver parameters
*
*******************************************************************/


/******************************************************************/

#define XPAR_D_LMB_BRAM_IF_CNTLR_BASEADDR 0x00000000
#define XPAR_D_LMB_BRAM_IF_CNTLR_HIGHADDR 0x00001FFF
#define XPAR_I_LMB_BRAM_IF_CNTLR_BASEADDR 0x00000000
#define XPAR_I_LMB_BRAM_IF_CNTLR_HIGHADDR 0x00001FFF
#define XPAR_SDRAM_CONTROLLER_BASEADDR 0x80000000
#define XPAR_SDRAM_CONTROLLER_HIGHADDR 0x80FFFFFF
#define XPAR_SYSTEM_MEMCON_BASEADDR 0xFFFF0000
#define XPAR_SYSTEM_MEMCON_HIGHADDR 0xFFFF01FF
#define XPAR_SYSTEM_MEMCON_MEM0_BASEADDR 0xFFE00000
#define XPAR_SYSTEM_MEMCON_MEM0_HIGHADDR 0xFFEFFFFF
#define XPAR_SYSTEM_MEMCON_MEM1_BASEADDR 0xFF000000
#define XPAR_SYSTEM_MEMCON_MEM1_HIGHADDR 0xFF7FFFFF

/******************************************************************/

#define XPAR_XUARTLITE_NUM_INSTANCES 1
#define XPAR_CONSOLE_UART_BASEADDR 0xFFFF2000
#define XPAR_CONSOLE_UART_HIGHADDR 0xFFFF20FF
#define XPAR_CONSOLE_UART_DEVICE_ID 0
#define XPAR_CONSOLE_UART_BAUDRATE 115200
#define XPAR_CONSOLE_UART_USE_PARITY 0
#define XPAR_CONSOLE_UART_ODD_PARITY 1
#define XPAR_CONSOLE_UART_DATA_BITS 8

/******************************************************************/

#define XPAR_XTMRCTR_NUM_INSTANCES 1
#define XPAR_SYSTEM_TIMER_BASEADDR 0xFFFF1000
#define XPAR_SYSTEM_TIMER_HIGHADDR 0xFFFF10FF
#define XPAR_SYSTEM_TIMER_DEVICE_ID 0

/******************************************************************/

#define XPAR_INTC_MAX_NUM_INTR_INPUTS 3
#define XPAR_INTC_SINGLE_BASEADDR 0xFFFF3000
#define XPAR_INTC_SINGLE_HIGHADDR 0xFFFF30FF
#define XPAR_XINTC_USE_DCR 0
#define XPAR_XINTC_NUM_INSTANCES 1
#define XPAR_SYSTEM_INTC_BASEADDR 0xFFFF3000
#define XPAR_SYSTEM_INTC_HIGHADDR 0xFFFF30FF
#define XPAR_SYSTEM_INTC_KIND_OF_INTR 0x00000002

/******************************************************************/

#define XPAR_SYSTEM_TIMER_INTERRUPT_MASK 0X000001
#define XPAR_CONSOLE_UART_INTERRUPT_MASK 0X000002
#define XPAR_EXTERNAL_INT_0_O_MASK 0X000004

/******************************************************************/

#define XPAR_XGPIO_NUM_INSTANCES 1
#define XPAR_OPB_GPIO_0_BASEADDR 0xFFFFA000
#define XPAR_OPB_GPIO_0_HIGHADDR 0xFFFFA0FF
#define XPAR_OPB_GPIO_0_DEVICE_ID 0

/******************************************************************/

#define XPAR_OPB_GPIO_LED_BASEADDR 0xFFFFA200

/******************************************************************/
