
/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 6.3 EDK_Gmm.12.3
* DO NOT EDIT.
*
* Copyright (c) 2004 Xilinx, Inc.  All rights reserved. 
* 
* Description: Driver parameters
*
*******************************************************************/


/******************************************************************/

#define XPAR_SYSTEM_MEMCON_MEM0_BASEADDR 0xF0E00000
#define XPAR_SYSTEM_MEMCON_MEM0_HIGHADDR 0xF0EFFFFF
#define XPAR_SYSTEM_MEMCON_MEM1_BASEADDR 0xF0000000
#define XPAR_SYSTEM_MEMCON_MEM1_HIGHADDR 0xF07FFFFF
#define XPAR_SDRAM_CONTROLLER_BASEADDR 0x00000000
#define XPAR_SDRAM_CONTROLLER_HIGHADDR 0x01FFFFFF
#define XPAR_OPB_GPIO_0_BASEADDR 0xF0FFA000
#define XPAR_OPB_GPIO_0_HIGHADDR 0xF0FFA0FF

/******************************************************************/

#define XPAR_XUARTLITE_NUM_INSTANCES 1
#define XPAR_CONSOLE_UART_BASEADDR 0xF0FF2000
#define XPAR_CONSOLE_UART_HIGHADDR 0xF0FF20FF
#define XPAR_CONSOLE_UART_DEVICE_ID 0
#define XPAR_CONSOLE_UART_BAUDRATE 115200
#define XPAR_CONSOLE_UART_USE_PARITY 0
#define XPAR_CONSOLE_UART_ODD_PARITY 1
#define XPAR_CONSOLE_UART_DATA_BITS 8

/******************************************************************/

#define XPAR_OPB_GPIO_LED_BASEADDR 0xF0FFA200

/******************************************************************/

#define XPAR_SPI_FLASH_BASEADDR 0xF0FF0000
#define XPAR_SPI_FLASH_HIGHADDR 0xF0FF01FF
#define XPAR_SPI_FLASH_DEVICE_ID 0
#define XPAR_SPI_FLASH_FIFO_EXIST 1
#define XPAR_SPI_FLASH_SPI_SLAVE_ONLY 0
#define XPAR_SPI_FLASH_NUM_SS_BITS 2

/******************************************************************/
